Principal IC Design Engineer

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Job Description:
Job Description:
The engineer in this position will join a team of highly competent chip design engineers involved in the implementation of high performance and low power IPs for complex digital systems.
Capable of presenting new ideas and concepts to Integration team, and display strong analytical skills
Provide technical assessment of projects and designs to Integration management team
Works closely with Architecture, RTL and Layout teams to understand design for STA, DFT and timing closure of complex digital circuits
Good team player able to work with other ASIC Design, Integration, Layout Engineers and managers across geography in a matrix organization
Job Requirements:
BSCS or BSEE or equivalent required, MSEE is a plus, with at least 10+ years of related experience
Strong experience in Synthesis, DFT, Static Timing Analysis, timing closure techniques with industry leading tools
Strong working knowledge of UPF, low power synthesis tools and techniques
Exposure to various formal verification tools and deep knowledge of debug skills
Strong working knowledge of low power verification tools.
Strong working knowledge of scripting languages (Perl, Tcl etc.)
Experience with Design for Test (DFT) tools and DFT schemes
Experience with complex SOC integration that include high speed interfaces
Familiarity with Development of design methodology, flow automation and improvements.
Knowledge of Physical design tools is a plus
Strong written and oral communication skills
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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