Semiconductor Validation Engineer HW

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All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability or protected veteran status.
Job Description:
An experienced test engineer is being sought for system test and system validation/qualification of high speed DRAM interfaces. The successful candidate will be part of system team and will participate in the definition of test plan and will perform all testing according to the plan. Within a concurrent engineering environment, the individual will be part of a larger team with system architects, ASIC engineers, other test engineers and SI engineers in creation of next generation broadband products. The candidate is ideally an expert in DDR DRAM technology and interface signaling with demonstrated experience in these areas.
Essential Duties and Responsibilities Include:
Creation of the characterization specification and validation criteria for all systems to test
Lead and perform DDR testing and DDR characterization/validation across PVT (Process-Voltage-Temperature)
Lead and perform JEDEC DDR Compliance testing with Keysight JEDEC Compliance suite.
Lead debugging effort, coordinate/perform the work and describe/show results when available.
Perform very high speed scope measurements (timing/voltage) on boards to be able to determine time/voltage margins
As part of a team, you will lead and participate in technical discussions within the immediate group and across functions, where evaluating and executing test and validation plans for all new and existing products
Job Requirements
Requires a BS degree in Electrical/Computer Engineering or a related discipline with at least 3 years of experience in chip industry
Expertise with DDR3, DDR4, LPDDR3 and LPDDR4 DRAM technologies and specifications
Proficient with lab equipment such as oscilloscopes (Keysight DDR tools and JEDEC DDR Compliance Suite)
Capable of presenting new results to management team.
Proficient to read/understand schematic and pcb layout design
Proficient with de-embedding methodology
Strong written and oral communication skills
The candidate for this position must be able to work independently, have the ability to put in place new procedures, and complete multiple parallel tasks on time.
Good team player able to work with other test engineers and managers across geography in a matrix organization.
Previous exposure to system & chip verification/validation is critical
Experience with system lab bring up and design validation on products
Proficient with de-solder and solder electronic SMT components on PCB
Experience with Agile/Oracle (Product Lifecycle Management Solution) Software is desired
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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